Spansion announces HyperBus Interface and HyperFlash NOR Memory devices

Spansion Inc. announced the release of its HyperBus Interface, meant to improve read performance while reducing the number of pins.

Apanish also announced the introduction of its first family of products based on this new interface, named Spansion HyperFlash NOR Memory devices, with read throughput of up to 333 megabytes per second. This is more than five times faster than ordinary Quad SPI flash currently available with one-third the number of pins of parallel NOR flash.

The Spansion HyperBus Interface will enable applications such as automotive instrument clusters, infotainment / navigation systems, advanced driver assistance systems (ADAS), hand-held displays, digital cameras, projectors, factory automation, medical diagnostic equipment, and home automation appliances.

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Spansion HyperBus Interface consists of an 8-pin address/data bus, a differential clock (2 signals), one Chip Select and a Read Data Strobe for the controller.

"This interface has the potential to deliver performance and space efficiency to a variety of hardware solutions, including: flash, RAM and peripheral devices. In addition, the Spansion HyperBus Interface provides a clear transition for 'SPI NOR-type' devices to migrate to higher density and higher speed previously only available through a parallel high pin-count NOR device," said Alan Niebel, CEO, Web-Feet Research .

Spansion HyperFlash Memory will initially include three densities: 128Mb, 256Mb and 512Mb, with the 512Mb devices sampling in the second quarter of 2014. 3V and 1.8V power-supply versions will be available, in a space-saving 8x6mm ball grid array (BGA) package.

The memory devices provide a migration path—from single Quad SPI to Dual Quad SPI to HyperFlash Memory—allowing system applications to be scaled to different levels of flash performance when paired with compatible controllers. This way, OEMs can offer different product models with a single design.


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