Samsung announced the first 3D Vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. The 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and SSDs.
Samsung's new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung's 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.
By making this CTF layer three-dimensional, the reliability and speed of the NAND memory have improved sharply. Samsung's new V-NAND achieves new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully developed. To do this, Samsung revamped its CTF architecture, which was first developed in 2006. In Samsung's CTF-based NAND flash architecture, an electric charge is temporarily placed in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighboring cells.
By making this CTF layer three-dimensional, the reliability and speed of the NAND memory have improved. The new 3D V-NAND shows not only an increase of a minimum of 2X to a maximum 10X higher reliability, but also twice the write performance over conventional 10nm-class floating gate NAND flash memory.
Also, one of the most important technological achievements of the new Samsung V-NAND is that the vertical interconnect process technology can stack as many as 24 cell layers vertically, using special technology that connects the layers electronically by punching holes from the highest layer to the bottom. With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling.