Synopsys announced the availability of Verification Compiler solution

Synopsys, Inc., specialised in providing software, IP and services used to accelerate innovation in chips and electronic systems, announced the availability of Verification Compiler solution.

Verification Compiler portfolio includes advanced debug, static and formal verification, simulation, verification IP and coverage closure. It offers a 5X performance improvement in debug efficiency, enabling SoC design and verification teams to create a complete functional verification flow with a single product.


Verification Compiler features formal verification, SoC connectivity checking, SoC-scale clock domain crossing (CDC) checking, X-propagation simulation, native low power simulation, and advanced verification planning and management. It also includes the entire portfolio of Synopsys' verification IP, with the corresponding test suites.

The new technology includes formal property checking, low power static checking, CDC checks, SoC connectivity checks, lint and sequential equivalence checking, being fully compatible with the Synopsys Design Compiler and Synopsys IC Compiler use model and flows.

Verification Compiler has debug capabilities built using technology from Synopsys' Verdi3, with new features such as Interactive Testbench (UVM-aware) Debug, Transaction Debug, HW/SW Debug, Power-Aware Debug, and Protocol-Aware Debug.Verification Compiler also includes three independent, concurrent keys (one key for all static and formal technologies, one key for simulation-related technologies, including all VIP, and one key for all debug technologies), enabling design teams to simultaneously perform multiple verification functions.

General availability of Verification Compiler is planned for December 2014. For now, the technology is under limited customer availability.

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